New generations of printed circuit board manufacturing technologies are pushing higher density components and signals into smaller and smaller board dimensions. A significant contributing factor of this trend is the ever decreasing package size of computer chips. The decrease in the physical dimensions of computer chips has impacted the hardware development and printed wiring assembly (PWA) manufacturing environments where access to component pins is required to debug and test circuit board components.
As shown in FIG. 1A, a logic analyzer system 100 is an example of a system that includes a standard tool used for debugging printed circuit boards. A logic analyzer system 100 comprises a logic analyzer 102 that includes a Central Processing Unit (CPU) 104 and memory 106. An input device 110 such as a keyboard and mouse, a display device 112 such as a Cathode Ray Tube (CRT) display and a computer readable medium device 116 such as a CD ROM drive that receives input from computer readable medium 114 are coupled via signal buses 105, 107 and 108 to CPU 104. Memory 106 such as Read Only Memory (ROM) and Random Accessible Memory (RAM) are coupled via signal bus 105 to CPU 104.
With Logic Analyzer 102, engineers and technicians can display and study on display device 112 via bus 108 the sequence of signals executed within printed circuit board 118. Engineers can analyze these signal patterns to determine if the logic is executing correctly or, if not, they can use the data to pinpoint where the fault is occurring.
Conventional logic analyzers, such as logic analyzer 102, require component pins for capturing digital signals to analyze circuit board components such as chips. Access to assembled printed circuit board signals provided by typical component pins generally requires a delicate and expensive logic analyzer chip adapter. For example, chip adapters 128 and 130 require pins to capture the signals originating from components such as a processor 120, a driver 124 for disk 130 and a memory 126. It is particularly difficult to access signals across a bus such as bus 122.
FIG. 1B shows in detail chip adapter 130 clamped to pins 206 and 208 for capturing signals originating from memory component 126 which is mounted to circuit board 118. Logic analyzer leads 204 and 202 are used for connecting cables extending from logic analyzer 102 to chip adapter 130.
Due to the small dimensions and limited space between components, a logic analyzer chip adapter is typically unable to obtain unimpeded access of test points and in some cases may become detached during testing, resulting in a less than reliable testing mechanism.
Further, because pin counts are increasing into the 200-700 range per component, it has become increasingly more difficult to correctly identity and attach an adapter to the correct set of pins. Accordingly, such analysis requires expensive and delicate chip adapters.
Another problem for conventional logic analyzers is the need to use a large assortment of cable attachments and probes between the printed circuit board under test and the logic analyzer. Such cable attachments and probes are generally difficult to assemble and maintain so that circuit board testing is error prone, laborious and time consuming. Because the trend is toward more complex circuit boards this problem will only worsen as signal/component densities increase.
For example, FIG. 2 shows a diagram of the logic analyzer's conventional method of retrieving signal information. Due to the density of components mounted to circuit board 118 and due to high pin counts, there may be a need as shown in FIG. 2 to overlap chip adapters 136, 134, 132, 130 and 128. One of ordinary skill in the art will recognize that use of multiple chip adapters can lead to errors and frustration in an attempt to set up the logic analyzer adapters and cables.
Another problem for testing PWA's is that new integrated circuit technology such as "Ball Grid Array Devices," as shown in FIG. 3A and 3B, are devices mounted to circuit boards that do not provide pins which are accessible for debugging purposes. In order to test such components, conventional logic analyzers attach to one or more pins of another component via a trace that connects to the ball grid array device under test. Since indirect testing adds additional testing variables, this type of testing is less exact than direct testing and is prone to errors.
For example, FIG. 3A shows an example ball grid array processor 302 mounted within mounting frame 300 to circuit board 118. The top accessible side 304 of processor 302 does not include pins. Hence, pins are not available for establishing a connection with a chip adapter. FIG. 3B shows the bottom side of processor 302 where only ball endpoints 308 are available. FIG. 3C shows a side view of ball grid array processor 302 having ball endpoints 308 at the bottom side is mounted to circuit board 118. Accordingly, neither the top nor bottom side of processor 302 provides pins that are accessible for logic analyzer 102 testing.
As a result, there has been a longfelt need for a logic analyzer probe board that provides a logic analyzer quick and efficient access of each signal across an electronic unit under test (UUT), minimizes exposure to human error in performing signal analysis, and maintains the signal integrity of the unit under test--requirements never previously met by conventional logic analyzer systems.